Eliminating substrate noise by an electrically isolated high-voltage I/O transistor

ABSTRACT

On the surface of a semiconductor material of a first conductivity type  101   a , a lateral MOS transistor  100  is described surrounded by a well  171  of the opposite conductivity type and, nested within the well, an electrical isolation region  102.  The semiconductor region  101   a  embedding this transistor has a resistivity higher than the remainder of the semiconductor material  101  and further contains a buried layer  160  of the opposite conductivity type. This layer  160  extends laterally to the wells  171,  thereby electrically isolating the near-surface portion of the semiconductor region from the remainder of the semiconductor material, and enabling the MOS transistor to operate as an electrically isolated high-voltage I/O transistor for circuit noise reduction, while having low drain junction capacitance.  
     In the first embodiment of the invention (FIG.  1 ), the buried layer  171  extends vertically deeper from the surface than the electrical isolation region  102,  thereby enabling a separate contact  106  to the electrically isolated near-surface portion  101   a  of the semiconductor region.

FIELD OF THE INVENTION

[0001] The present invention is related in general to the field ofelectronic systems and semiconductor devices, and more specifically tostructures and fabrication methods for an electrically isolatedhigh-voltage transistor operable to eliminate substrate noise.

DESCRIPTION OF THE RELATED ART

[0002] In mixed-signal integrated circuits (ICs), analog circuits aredesigned on the same semiconductor chip together with digital circuits.Consequently, since analog circuits share the same substrate withhigh-speed digital circuits, electrical noise created by the high-speedoperation is coupled between the circuits and may affect the performanceof the analog circuits. As the frequency of the operational digitalcircuit increases, and transistor dimensions are reduced, the effect ofthe noise coupling is becoming more and more serious.

[0003] A recent study of the substrate noise and several types of guardrings designed for noise rejection, has been published by Hwan-Mei Chenget al. (“A Study of Substrate Noise and Noise-rejection-efficiency ofGuard-ring in Monolithic Integrated Circuits”, IEEE Trans. 2000,pp.123-128). Unfortunately, the proposed substrate noise remediesinclude designs requiring additional silicon real estate area, oradditional photomask steps. The costs connected with these additionaldesign and fabrication steps make them economically unattractive.

[0004] An urgent need has, therefore, arisen for a coherent, low-costmethod of blocking substrate noise in mixed-signal ICs. The methodshould further enhance IC electrical performance, mechanical stabilityand high reliability. The fabrication method should be simple, yetflexible enough for different semiconductor product families and a widespectrum of design and process variations. Preferably, these innovationsshould be accomplished without extending production cycle time, andusing the installed equipment, so that no investment in newmanufacturing machines is needed.

SUMMARY OF THE INVENTION

[0005] On the surface of a semiconductor material of a firstconductivity type, a lateral MOS transistor is described surrounded by awell of the opposite conductivity type and, nested within the well, anelectrical isolation region. The semiconductor region embedding thistransistor has a resistivity higher than the remainder of thesemiconductor material and further contains a buried layer of theopposite conductivity type. This layer extends laterally to the wells,thereby electrically isolating the near-surface portion of thesemiconductor region from the remainder of the semiconductor material,and enabling the MOS transistor to operate as an electrically isolatedhigh-voltage I/O transistor for circuit noise reduction, while havinglow drain junction capacitance.

[0006] It is a technical advantage of the present invention that thereare several options for designing the buried layer and the electricalcontact to the resulting isolated base of the MOS transistor:

[0007] In the first embodiment of the invention, the buried layerextends vertically deeper from the surface than the electrical isolationregion, thereby enabling a separate contact to the electrically isolatednear-surface portion of the semiconductor region.

[0008] In the second embodiment of the invention, the buried layerextends vertically from the surface not as deep as the electricalisolation region, thereby enabling contacts to the electrically isolatednear-surface portion of the semiconductor region in the shape of abody-tied source. This body-tied source is configured to provide adual-function contact region to the MOS transistor source, and to theelectrically isolated near-surface portion of the semiconductor region.

[0009] In the third embodiment of the invention, the buried layerextends vertically from the surface not as deep as the electricalisolation region, thereby enabling contacts to the electrically isolatednear-surface portion of the semiconductor region in the shape of anangular-structured gate of the MOS transistor. This angular-structuredgate is configured to include an H-shape or a T-shape such that itsdirectly adjacent regions provide contacts to the source, drain, andnear-surface portion of the semiconductor region.

[0010] It is an essential aspect of the invention to use the photomaskstep, which is needed for implanting the low energy ions in order tocreate the extended source and drain, for the additional process step ofimplanting at high energy and high dose the ions needed to create theburied layer. This economical feature renders the additional high-energyion implant step and thus the formation of an electrically isolatedhigh-voltage I/O transistor exceedingly inexpensive.

[0011] Another aspect of the invention is that the high energy/high doseion implant step transforms the electrically isolated region of thefirst conductivity type into a region of higher resistivity compared tothe remainder of the semiconductor material of the first conductivitytype.

[0012] The present invention is equally applicable to nMOS and pMOStransistors; the conductivity types of the semiconductor and the ionimplant types are simply reversed.

[0013] The technical advances represented by the invention, as well asthe aspects thereof, will become apparent from the following descriptionof the preferred embodiments of the invention, when considered inconjunction with the accompanying drawings and the novel features setforth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a schematic cross section of an electrically isolatedhigh voltage I/O nMOS transistor as provided by the first embodiment ofthe invention.

[0015]FIG. 2 is a schematic cross section of an electrically isolatedhigh voltage I/O nMOS transistor as Provided by the second and thirdembodiments of the invention.

[0016]FIG. 3 is a schematic top view of the electrically isolated MOStransistor according to the second embodiment of the invention,depicting the source contact in the form of a body-tied-contact(alternating p-n-p-n doped regions).

[0017]FIG. 4 is a schematic top view of the electrically isolated nMOStransistor according to the third embodiment of the invention, depictingthe gate in H-form in order to provide contact to the isolated p-well(body contact).

[0018]FIG. 5 is an example of a plot of the doping profiles under thegate of an nMOS transistor before and after the high-energy n-typeimplant according to the second and third embodiments of the invention.

[0019]FIG. 6A plots the computer-generated doping profiles under thegate of an nMOS transistor after a high-energy n-type and p-typeimplants according to the invention.

[0020]FIG. 6B plots the computer-generated doping profiles under sourceand drain of an nMOS transistor after a high-energy n-type and p-typeimplants according to the invention.

[0021]FIG. 7 shows the cross section of an nMOS transistor with thecomputer-generated conductivity regions after a high-energy n-type andp-type implants according to the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention is related to U.S. patent application Ser.No. 60/263,619, filed on Jan. 23, 2001 (Salling et al., “Structure andMethod of MOS transistor having Increased Substrate Resistance”).

[0023] In a typical integrated circuit (IC), an output buffer drives thevoltage on an output pad (I/O pad) by one or more pMOS transistorsconnected between pad and positive power supply voltage bus, and one ormore nMOS transistors connected between pad and ground. There areseveral reasons why it is desirable to electrically isolate an outputbuffer's nMOS transistors from the substrate.

[0024] When the large output nMOS transistors of an output switch are inoperation, they generate substrate current pulses due to hole generationat the drain junction, and capacitive displacement currents at the drainjunction's parasitic capacitance to the substrate. This substratecurrent constitutes noise for any sensitive, low-noise analog inputsintegrated on the same chip.

[0025] The substrate hole current can also cause latch-up.

[0026] Another source of substrate current occurs when the pad of anoutput buffer transits to a negative voltage during some transient. Forexample, this may be caused by an undershot of the output buffer, or bya transient on incoming signals in a bi-directional pad (input+outputpad). This substrate electron current can cause latch-up, and it maycause noise on analog inputs.

[0027] It is cumbersome in conventional technology to achieve thedesirable electrical isolation of the nMOS transistors because of therequirement of an additional photomask step. The invention eliminatesthis hurdle. FIGS. 1, 2, 3, and 4 show the resulting embodiments of ICstructures according to the invention, and FIG. 5 gives an example of adoping profile under the transistor gate illustrating the method toaccomplish the desired electrical isolation of the nMOS transistor.While the examples depicted embody the experimental conditions for annMOS transistor, analogous considerations hold for the conditions of apMOS transistor.

[0028]FIG. 1 shows in simplified and schematic (not to scale) manner asmall portion of an IC, generally designated 100, having on its surfacea high-voltage I/O MOS transistor isolated by a buried layer. Theinvention applies to nMOS as well as pMOS transistors fabricated intosemiconductor material 101, often referred to as the substrate. Here,the substrate may comprise a p-type semiconductor wafer, onto which, forsome devices, an epitaxial layer, also of p-type doping, has beendeposited. (For clarity, the description and discussion of the inventionwill be for a p-type semiconductor as the “first” conductivity type.However, the invention is also applicable, if an n-type substrate isused as the first conductivity type material). The semiconductormaterial may be silicon, silicon germanium, gallium arsenide or anyother semiconductor material used in IC fabrication.

[0029] The resistivity of the semiconductor substrate 101, into whichthe MOS transistor is fabricated, ranges from about 1 to 50 Ωcm (this isalso the resistivity of the epitaxial layer). Frequently, the materialclose to the MOS transistor may be generated as a well of the firstconductivity type, in the example of FIG. 1 a p-well.

[0030] A silicon dioxide isolation trench 102 (preferably 350 nm deep)has been created to surround the lateral MOS transistor; it defines theactive area of the lateral transistor. For the gate 103 of the MOStransistor, polysilicon or another conductive material is usuallychosen; its thickness 103 a is commonly between 140 and 180 nm, and thewidth 103 b between 0.2 and 1.0 μm. The gate insulator 104 (silicondioxide, nitrided SiO2, or others) has a physical thickness between 1and 10 nm.

[0031]FIG. 1 shows an additional silicon dioxide isolation trench 170,which defines the lateral extent of the deep well 171 on the surface.This well is of the conductivity type opposite to the “first”conductivity type; in the example of FIG. 1, well 171 is an n-well; itis contacted by n+-region 172. The n-well completely surrounds the nMOStransistor, and it is reaches deep from the surface into thesemiconductor material 101 of the first conductivity type (p-type inFIG. 1).

[0032]FIG. 1 shows a deep source 110 and an extended source 111, furthera deep drain 112 and an extended drain 113. The extended source anddrain are prepared by low-energy, shallow implants (depth typicallybetween 25 and 40 nm), the deep source and drain by medium-energyimplants (depth typically between 100 and 140 nm) as part of the processflow discussed later. For the fabrication by ion implantation, a window130 a in a photoresist layer 130 is used; window 130 a determines thelateral extent and active area of the MOS transistor.

[0033] The same photoresist and window are used for the high-energy andhigh dose implant 140 of the present invention. This implant isperformed for creating the buried layer 160 within the opening of window130 a. In FIG. 1, buried layer 160 is n-type. As further consequence ofthe high energy ion implant 140, the p-type semiconductor materialportion 101 a between surface and the buried layer 160 acquires aresistivity higher than the resistivity of the remainder 101 of thep-type semiconductor material.

[0034] Laterally, buried layer 160 extends to the n-well 171.Consequently, the buried layer electrically isolates the near-surfaceportion 101 a of the p-type material from the remainder 101 of thesemiconductor material. The nMOS transistor is completely positionedwithin this isolated portion 101 a and is thus an electrically isolatedtransistor, operable as a high-voltage I/O transistor which does notcreate substrate noise for the IC. Due to the partially counterdopedp-type regions under source and drain, the transistor has low drainjunction capacitance.

[0035] Vertically, the position of the buried layer 160 relative to thesurface depends on the energy of the implanted ions. In the firstembodiment of the invention, which is depicted in FIG. 1, the buriedlayer edge 160 a nearest the surface is deeper, i.e. farther away, fromthe surface than the bottom of the electrical isolation regions 102.This fact results in an electrically isolated p-type region 101 acontinuous under one portion of isolation region 102; this connectingportion is marked 101 b in FIG. 1. The thickness 101 c of the connectingportion is a function of the energy of the implanted n-type ions.

[0036] This continuity feature, in turn, enables a separate p+-contact106 to the electrically isolated near-surface portion 101 a of thep-type semiconductor region. The geometrical extent of the contactregion 106 is limited by an additional isolation region 107, whichsimultaneously serves as one of the limiting “markers” for n-well 171.

[0037] It may be mentioned that the thickness of the photoresist layer130 is larger than the thickness solely required to block the lowerenergy implants. Preferably, the photoresist layer thickness is between1.5 and 2.0 μm. If the high-energy implant accompanies the medium-energyimplant, non-conductive sidewalls 150 are typically present as part ofthe gate structure.

[0038] For nMOS transistors, the semiconductor of the first conductivitytype (p-type) (including any epitaxial layer) has dopant speciesselected from a group consisting of boron, aluminum, gallium, andindium. Source, drain, their extensions, and the buried layer within thesemiconductor of the first conductivity type have a dopant speciesselected from a group consisting of arsenic, phosphorus, antimony, andbismuth.

[0039] For pMOS transistors, the semiconductor of the first conductivitytype (n-type) has dopant species selected from a group consisting ofarsenic, phosphorus, antimony, and bismuth. Source, drain, theirextensions, and the buried layer within the semiconductor of the firstconductivity type have a dopant species selected from a group consistingof boron, aluminum, gallium, indium, and lithium.

[0040] As a consequence of the fabrication process flow, the isolatedp-type region 101 a is shallower under the poly gate 103 by a measurabledistance 101 d. The thickness of distance 101 c depends on the energy ofthe implanted n-type ions. Further, the net n-type doping of the buriedlayer 160 is slightly higher under the poly gate and can be measured byimaging the 2-dimensional profile of the buried n-type layer, forinstance by using a 2-dimensional SIMS technique after cleaving anddiode-etching the sample.

[0041] As for electrical circuit connections, drain 112 is connected tothe I/O pad as the high voltage contact, source 110 is connected to bodycontact 106 and both to Vss or ground, and n-well contact 172 (and thusthe buried layer 160) to Vdd.

[0042] The schematic cross section of FIG. 2 illustrates the buriedlayer for the second and third embodiments of the invention. The maindifference compared to the structure depicted in FIG. 1 is the reducedvertical depth of the buried layer 260 from the semiconductor surface,brought about by a reduced energy of the implanted n-type ions 240.Since the depth 202 a of the isolation trench 202 is preferably 350 nm,the buried layer edge 260 a is less than 350 nm away from the surface.The buried layer 260, however, still extends laterally to the n-well 271(which is contacted by n+-region 272).

[0043] Consequently, the embodiment of FIG. 2 does no longer exhibit acontinuity of the isolated p-type region 201 a beyond the isolationtrench 202. The constraint of isolated region 201 a necessitatesspecific means to establish the electrical contact to isolated region201 a. The specific means is provided by specific structures of source210 of the MOS transistor.

[0044] In the example of FIG. 2, the nMOS transistor consists of source210 with 211, drain 212 with 213, gate 203, and gate insulation 204.

[0045] In the second embodiment of the invention, the electrical contactto the isolated region 201 a is provided by the design of source 210 asa “body-tied source”. The structure of this body-tied-to-source isschematically illustrated in the top view of the transistor in FIG. 3.Equal numbers refer to equal entities in FIGS. 2 and 3. The n+ contact272 to the n-well (and thus the buried n-type layer) completelysurrounds the nMOS transistor; n+ contact 272 is electrically connectedto Vdd. Nested within the n+ contact is the shallow trench isolation202. Gate 203 of the nMOS transistor may be designed in a variety ofdifferent shapes convenient for layout and electrical connections.N+-type drain contact region 212 is electrically connected to the I/Opad as the high voltage contact. The (n+-type) source contact regions210 alternate laterally with the (p+-type) body contact regions 306 (notshown in FIG. 2). Overlaid metal contact layer 310 joins the electricalcontacts to source and body and provides the electrical connection toVss.

[0046] In the third embodiment of the invention, the electrical contactto the isolated region 201 a (the body) is provided by a designpracticed in the silicon-on-insulator technology: The gate is structuredin an “H”-shape or a “T”-shape. An example is illustrated in theschematic top view of FIG. 4 for an H-shaped gate of an nMOS transistor.Equal numbers refer to equal entities in FIGS. 2 and 4. The n+ contact272 to the n-well (and thus the buried n-type layer) completelysurrounds the nMOS transistor; n+ contact 272 is electrically connectedto Vdd. Nested within the n+ contact is the shallow trench isolation202. Gate 203 of the nMOS transistor may be designed in a variety ofdifferent shapes such as H-shape (as Shown in FIG. 4) or T-shape.N+-type drain contact region 212 is electrically connected to the I/Opad as the high voltage contact. N+-type source contact region 210 isconnected to Vss. P+-type body contacts 406 are also connected to Vss.

[0047] By way of example for an nMOS transistor as shown in FIG. 2, FIG.5 depicts the computer-generated doping profiles under the gate, asresulting from the high-energy n-doping implant of the presentinvention. The ordinate plots the doping concentrations on logarithmicscale, and the abscissa shows the penetration depths into thesemiconductor surface, expressed in μm. FIG. 5 shows the starting boronconcentration (curve 502) and the implanted phosphorus concentration(curve 501). as needed for creating the buried n-type layer at a depthas illustrated in FIG. 2. Further, the resulting net doping isillustrated (curve 503). The phosphorus implant is selected at theenergy of 500 keV at the dose of 2.0 E13 cm-2. This creates the buriedn-type layer as depicted in FIG. 2, with the peak penetration issomewhat less deep under the surface than in FIG. 1 (an energy of about675 keV at the same dose of 2.0E13 cm-2 is needed for the penetration ofFIG. 1). In the region 510, stretching approximately from 0.19 μm to0.53 μm depth, the phosphorus doping overcompensates the boron doping(curve 502), leading to the buried n-type region embedded within thep-type semiconductor material.

[0048] A computer simulation of a similar preferred ion implantcondition for creating the buried layer is displayed for the conditionsof:

[0049] phosphorus implant energy 500 keV, dose 4·10E13;

[0050] boron implant energy 100 keV, dose 1·10E13.

[0051]FIG. 6A plots the resulting doping concentrations under the gate,and FIG. 6B plots the concentrations under source and drain. In bothfigures, a junction has been created where the phosphorus doping curvesintersect with the boron implant curves. In FIG. 6A, phosphorus dopingcurve 601 intersects with boron doping curve 602 at points 603 and 604.In the region 610, stretching approximately from 0.22 to 0.62 μm depth,the phosphorus doping overcompensates the boron doping, leading to theburied n-type region embedded within the p-type semiconductor material.In FIG. 6B, phosphorus doping curve 621 intersects with boron dopingcurve 622 at points 623 and 624. In region 640, stretching approximatelyfrom 0.45 μm to 0.68 μm depth, the phosphorus doping overcompensates theboron doping, leading to the buried n-type region.

[0052] In summary, it can be seen that the buried layer continues fromthe region under the gate to the regions under source and drain, untilthe buried layer merges with the n-wells. There is a slight shift indepth, as indicated schematically in FIGS. 1 and 2 and morerealistically by the computer simulations in FIG. 7. The nMOS transistorcross section of FIG. 7 shows above the semiconductor surface 701 thegate 702 and the non-conductive side-walls 703, and under the surfacethe buried p-type region 704, the n-type source 705 and drain 706, andthe buried n-layer 707. Buried layer 707 has been created by thehigh-energy n-type ion implant according to the invention; it stretchescloser to the surface (and is thicker) under the gate 702, but iscontinuous from source to drain where it connects to the n-wells (notshown in FIG. 7).

[0053] It is a technical advantage of the present invention that thelocation, peak and depth of the buried layer can be precisely controlledby employing a high-energy, low-dose implant of p-doping ions inconjunction with the high-energy n-doping implant. In the preferredembodiment, the ion energy is between 70 and 140 keV, and the dosebetween 5·10E12 to 5·10E13. The effect of such implant can readily bededuced from FIGS. 6A, 6B and 7.

[0054] The method of fabricating a buried n-type layer connecting twon-wells in a p-type semiconductor surface region having an increasedresistivity relative to a p-type semiconductor sub-surface regioncomprises the following process steps (analogous process steps apply forthe fabrication of a buried p-type layer):

[0055] depositing a photoresist layer over the surface of the p-typesemiconductor sub-surface region, and opening a window in the layer overthe surface region between the n-wells; and

[0056] implanting, at high energy (about 400 to 700 keV) and high dose(about 8·10E12 to 8·10E13 cm-2), n-type ions into the p-typesemiconductor through the window, creating a deep region (depth of morethan 200 nm) having a net n-type doping between, and continuous with,said n-wells, and further creating a p-region having a dopingconcentration lower than that of the sub-surface p-type semiconductorregion.

[0057] The method of fabricating an electrically isolated high-voltageI/O nMOS transistor in the surface of p-type semiconductor materialcomprises the following process steps (analogous process steps apply forthe fabrication of a pMOS transistor):

[0058] forming two nested pairs of non-conductive electrical isolationregions into the p-type semiconductor material, the inner pair definingthe lateral boundaries of the nMOS transistor active area, and the outerpair defining the area between n-wells;

[0059] implanting p-doping or n-doping ions to adjust the backgrounddoping level of the sub-surface region of the p-type semiconductormaterial; after the background doping adjustment implant, the p-typesemiconductor has a peak doping concentration between 4·10E17 and1·10E18 cm-3;

[0060] forming n-wells into the adjusted p-type semiconductor material;

[0061] depositing over the surface a layer of insulating materialsuitable as gate dielectric, covering the transistor area;

[0062] depositing a layer of poly-silicon or other conductive materialonto the insulating layer;

[0063] protecting a portion of the poly-silicon and etching theremainder thereof, defining the gate area of the transistor;

[0064] depositing a first photoresist layer and opening a windowtherein, exposing the surface of the area between the outer isolationregions;

[0065] implanting, at low energy, n-doping ions into the exposed surfacearea, creating shallow n-doped layers (depth between 10 and 50 nm) underthe surface (peak concentration from about 5·10E17 to 5·10E20 cm-3),suitable as extended source and drain of the transistor;

[0066] implanting, at high energy (400 to 700 keV) and high dose 8·10E12to 8·10E13 cm-2), n-doping ions into the exposed surface area, creatinga deep region (depth more than 200 nm) under the surface having a netn-type doping between, and continuous with, the n-wells; the peakconcentration of the implanted ions is at a different depth than that ofthe p-type semiconductor in order to overcompensate the p-type dopingand to create the region of the opposite conductivity type;

[0067] and further creating a p-region having a doping concentrationlower than that of the adjusted subsurface p-type semiconductor region(peak concentration of about 1 to 6 E1017 cm-3 below the p-n junctionsof the deep source and drain regions;

[0068] removing the first photoresist layer;

[0069] depositing conformal insulating layers of an insulator, such assilicon nitride or silicon dioxide, over the surface and directionalplasma etching the insulating layers so that only side walls around thepoly-silicon gate remain;

[0070] depositing a second photoresist layer and opening a windowtherein, exposing the surface of the area between the outer isolationregions;

[0071] implanting, at medium energy, n-doping ions into the exposedsurface area, creating an n-doped region (peak concentration from about5·E19 to 5·10E20 cm-3) that extends to a medium depth (between 50 and 20nm) under said surface, suitable as deep source and drain of thetransistor;

[0072] removing the second photoresist layer; and

[0073] forming an electrical contact region to the p-region of lowerdoping concentration.

[0074] If desirable, an additional process step can be added after thehigh-energy n-type implant in order to control precisely the location,peak and depth of the buried layer:

[0075] implanting, at high energy and low dose, p-doping ions.

[0076] Dependent on the depth of the buried n-type layer from thesurface, the method of forming the electrical contact is selected fromthe following processes:

[0077] Forming a p+-region as contact region to the isolated p-typeregion close to, but electrically isolated from the source of the nMOStransistor; or

[0078] Forming a body-tied source providing a dual-function contactregion to the nMOS transistor source and to the electrically isolatednear-surface portion of the isolated p-type region; or

[0079] Forming an angular-structured gate, configured to include anH-shape or a T-shape such that its directly adjacent regions providecontacts to the source, drain and near-surface portion of the isolatedp-type region.

[0080] For fabricating a pMOS transistor according to the method of thepresent invention, the flow of the above process steps applies inanalogous fashion with a reversal of conductivity types.

[0081] While this invention has been described in reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiments, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. As an example, the method may comprise steps ofannealing the high and/or medium energy implants at elevatedtemperature. As another example, the process steps may be modified byimplanting the n-doping ions at high energy after the process step ofimplanting the n-doping ions at medium energy when the buried layer isshallow. It is therefore intended that the appended claims encompass anysuch modifications or embodiments.

We claim:
 1. An integrated circuit fabricated in semiconductor materialof a first conductivity type, said circuit having at the surface atleast one lateral MOS transistor surrounded by an electrical isolationregion, comprising: a source and a drain, each having at the surface aregion of the opposite conductivity type extending to the centrallylocated gate, defining the active area of said transistor; a well ofopposite conductivity type surrounding said source and drain, extendingfrom said surface deep into said semiconductor material of said firstconductivity type; a semiconductor region within said semiconductormaterial of said first conductivity type surrounded by said well, saidsemiconductor region having a resistivity higher than the remainder ofsaid semiconductor material; and a layer of said opposite conductivitytype buried in said semiconductor region; said layer extending laterallyto said wells, thereby electrically isolating the near-surface portionof said semiconductor region from the remainder of said semiconductormaterial, and enabling said MOS transistor to operate as an electricallyisolated high-voltage I/O transistor for circuit noise reduction, whilehaving low drain junction capacitance; said layer extending verticallydeeper from said surface than said electrical isolation region, therebyenabling a separate contact to said electrically isolated near-surfaceportion of said semiconductor region.
 2. The circuit according to claim1 wherein said semiconductor material is selected from a groupconsisting of silicon, silicon germanium, gallium arsenide, and anyother semiconductor material used in integrated circuit fabrication. 3.The circuit according to claim 1 wherein said semiconductor of the firstconductivity type is made of p-type silicon in the resistivity rangefrom about 1 to 50 Ωcm, and said source, drain, wells, and buried layerare made of n-type silicon.
 4. The circuit according to claim 1 whereinsaid semiconductor of the first conductivity type is a semiconductorepitaxial layer.
 5. The circuit according to claim 1 wherein saidsemiconductor of the first conductivity type has a dopant speciesselected from a group consisting of boron, aluminum, gallium, andindium, while said source, drain, their extensions, and said buriedlayer have a dopant species selected from a group consisting of arsenic,phosphorus, antimony, and bismuth.
 6. The circuit according to claim 1wherein said semiconductor of the first conductivity type is made ofn-type silicon in the resistivity range from about 5 to 50 Ωcm, and saidsource, drain, and their extensions are made of p-type silicon.
 7. Thecircuit according to claim 1 wherein said semiconductor of the firstconductivity type has a dopant species selected from a group consistingof arsenic, phosphorus, antimony, bismuth, and lithium, while saidsource, drain, their extensions, and said buried layer have a dopantspecies selected from a group consisting of boron, aluminum, gallium,indium, and lithium.
 8. An integrated circuit fabricated insemiconductor material of a first conductivity type, said circuit havingat the surface at least one lateral MOS transistor surrounded by anelectrical isolation region, comprising: a source and a drain, eachhaving at the surface a region of the opposite conductivity typeextending to the centrally located gate, defining the active area ofsaid transistor; a well of opposite conductivity type surrounding saidsource and drain, extending from said surface deep into saidsemiconductor material of said first conductivity type; a semiconductorregion within said semiconductor material of said first conductivitytype surrounded by said well, said semiconductor region having aresistivity higher than the remainder of said semiconductor material;and a layer of said opposite conductivity type buried in saidsemiconductor region; said layer extending laterally to said wells,thereby electrically isolating the near-surface portion of saidsemiconductor region from the remainder of said semiconductor material,and enabling said MOS transistor to operate as an electrically isolatedhigh-voltage I/O transistor for circuit noise reduction, while havinglow drain junction capacitance; said layer extending vertically fromsaid surface not as deep as said electrical isolation region, therebyenabling contacts to said electrically isolated near-surface portion ofsaid semiconductor region in the shape of body-tied source or ofangular-structured gate.
 9. The circuit according to claim 8 whereinsaid body-tied source is configured to provide a dual-function contactregion to said MOS transistor source, and to said electrically isolatednear-surface portion of said semiconductor region.
 10. The circuitaccording to claim 8 wherein said angular-structured gate of said MOStransistor is configured to include an H-shape or a T-shape such thatits directly adjacent regions provide contacts to said source, drain,and near-surface portion of said semiconductor region.
 11. A method offabricating a buried n-type layer connecting two n-wells in a p-typesemiconductor region, electrically isolating the near-surface p-typesemiconductor portion suitable for fabricating a high-voltage I/O nMOStransistor, comprising the steps of: depositing a photoresist layer overthe surface of said p-type semiconductor region, and opening a window insaid layer, exposing the surface area between said n-wells; implanting,at low energy, n-doping ions through said window, creating shallown-doped layers under said surface, suitable as extended source and drainof said transistor; and implanting, at high energy and high dose,n-doping ions into said p-type semiconductor through said window,creating a deep region having a net n-type doping between, andcontinuous with, said n-wells, and further creating a near-surfacep-region having a doping concentration lower than that of the remainderof said p-type semiconductor region.
 12. A method of fabricating anelectrically isolated high-voltage I/O nMOS transistor in the surface ofp-type semiconductor material, comprising the steps of: forming twonested pairs of non-conductive electrical isolation regions into saidp-type semiconductor material, the inner pair defining the lateralboundaries of said nMOS transistor active area, and the outer pairdefining the area between n-wells; implanting p-doping or n-doping ionsto adjust the background doping level of the sub-surface region of saidp-type semiconductor material; forming n-wells into said adjusted p-typesemiconductor material; depositing over said surface a layer ofinsulating material suitable as gate dielectric, covering saidtransistor area; depositing a layer of poly-silicon or other conductivematerial onto said insulating layer; protecting a portion of saidpoly-silicon and etching the remainder thereof, defining the gate areaof said transistor; depositing a first photoresist layer and opening awindow therein, exposing the surface of said area between said outerisolation regions; implanting, at low energy, n-doping ions into saidexposed surface area, creating shallow n-doped layers under saidsurface, suitable as extended source and drain of said transistor;implanting, at high energy and high dose, n-doping ions into saidexposed surface area, creating a deep region under said surface having anet n-type doping between, and continuous with, said n-wells, andfurther creating a p-region having a doping concentration lower thanthat of the remainder of said adjusted p-type region; removing saidfirst photoresist layer; depositing conformal insulating layers of aninsulator, such as silicon nitride or silicon dioxide, over said surfaceand directional plasma etching said insulating layers so that only sidewalls around the poly-silicon gate remain; depositing a secondphotoresist layer and opening a window therein, exposing the surface ofsaid area between said outer isolation regions; implanting, at mediumenergy, n-doping ions into said exposed surface area, creating ann-doped region that extends to a medium depth under said surface,suitable as deep source and drain of said transistor; removing saidsecond photoresist layer; and forming an electrical contact region tosaid p-region of lower doping concentration.
 13. The method according toclaim 12 further including the process step of implanting, at highenergy and low dose, p-doping ions for controlling the location andextent of said deep n-type region.
 14. The method according to claim 12further including the process step of forming a p+-region as saidelectrical contact region to said p-region of lower dopingconcentration, said p+-region located close to, but electricallyisolated from, the source of said nMOS transistor.
 15. The methodaccording to claim 12 further including the process step of forming abody-tied source providing a dual-function contact region to said nMOStransistor source and to said electrically isolated near-surface portionof said semiconductor region.
 16. The method according to claim 12further including the process step of forming an angular-structuredgate, configured to include an H-shape or a T-shape such that itsdirectly adjacent regions provide contacts to said source, drain, andnear-surface portion of said semiconductor region.
 17. The methodaccording to claim 12 wherein the thickness of said first photoresistlayer is larger than a thickness solely required to block saidlow-energy ion implant.
 18. The method according to claim 12 furthercomprising the step of annealing said high energy implant at elevatedtemperature.
 19. The method according to claim 12 comprising themodified process step of implanting said n-doping ions at high energyafter said process step of implanting said n-doping ions at mediumenergy.
 20. The method according to claim 12 wherein said p-typesemiconductor has a peak doping concentration between 4·10E17 and1·10E18 cm-3 after said background doping adjustment implant.
 21. Themethod according to claim 12 wherein said implanting of low energy ionscomprises ions having an energy suitable for creating the junction at adepth between 10 and 50 nm, and a peak concentration from about 5·10E17to 5·10E20 cm-3.
 22. The method according to claim 12 wherein saidimplanting of medium energy ions comprises ions having an energysuitable for creating the junction at a depth between 50 and 200 nm, anda peak concentration from about 5·10E19 to 5·10E20 cm-3.
 23. The methodaccording to claim 12 wherein said implanting of high energy ionscomprises ions selected in the energy range from about 400 to 700 keVsuch that the peak concentration is at a different depth than that ofthe p-type semiconductor, and in the dose range of about 8·E12 to8·10E13 cm-2 to overcompensate the p-type semiconductor doping and tocreate a region of the opposite conductivity type at a depth of morethan 200 nm.
 24. The method according to claim 12 wherein said netp-type doping of low concentration comprises a peak concentration ofabout 1 to 6 E17 cm-3 below the p-n junctions of said transistor's deepsource and drain regions.
 25. A method of fabricating a buried p-typelayer connecting two p-wells in an n-type semiconductor region,electrically isolating the near-surface n-type semiconductor portionsuitable for fabricating a high-voltage I/O pMOS transistor, comprisingthe steps of: depositing a photoresist layer over the surface of saidn-type semiconductor region, and opening a window in said layer,exposing the surface area between said p-wells; implanting, at lowenergy, p-doping ions through said window, creating shallow p-dopedlayers under said surface, suitable as extended source and drain of saidtransistor; and implanting, at high energy and high dose, p-doping ionsinto said n-type semiconductor through said window, creating a deepregion having a net p-type doping between, and continuous with, saidp-wells, and further creating a near-surface n-region having a dopingconcentration lower than that of the remainder of said n-typesemiconductor region.
 26. A method of fabricating an electricallyisolated high-voltage I/O pMOS transistor in the surface of n-typesemiconductor material, comprising the steps of: forming two nestedpairs of non-conductive electrical isolation regions into said n-typesemiconductor material, the inner pair defining the lateral boundariesof said pMOS transistor active area, and the outer pair defining thearea between p-wells; implanting n-doping or p-doping ions to adjust thebackground doping level of the sub-surface region of said n-typesemiconductor material; forming said p-wells into said adjusted n-typesemiconductor material; depositing over said surface a layer ofinsulating material suitable as gate dielectric, covering saidtransistor area; depositing a layer of poly-silicon or other conductivematerial onto said insulating layer; protecting a portion of saidpoly-silicon and etching the remainder thereof, defining the gate areaof said transistor; depositing a first photoresist layer and opening awindow therein, exposing the surface of said area between said outerisolation regions; implanting, at low energy, p-doping ions into saidexposed surface area, creating shallow p-doped layers under saidsurface, suitable as extended source and drain of said transistor;implanting, at high energy and high dose, p-doping ions into saidexposed surface area, creating a deep region under said surface having anet p-type doping between, and continuous with, said p-wells, andfurther creating an n-region having a doping concentration lower thanthat of the remainder of said adjusted n-type region; removing saidfirst photoresist layer; depositing conformal insulating layers of aninsulator, such as silicon nitride or silicon dioxide, over said surfaceand directional plasma etching said insulating layers so that only sidewalls around the poly-silicon gate remain; depositing a secondphotoresist layer and opening a window therein, exposing the surface ofsaid area between outer isolation regions; implanting, at medium energy,p-doping ions into said exposed surface area, creating a p-doped regionthat extends to a medium depth under said surface, suitable as deepsource and drain of said transistor; removing said second photoresistlayer; and forming an electrical contact region to said n-region oflower doping concentration.
 27. The method according to claim 26 furtherincluding the process step of implanting, and high energy and low dose,n-doping ions for controlling the location and extent of said deepp-type region.
 28. The method according to claim 26 further includingthe process step of forming a n+-region as said electrical contactregion to said n-region of lower doping concentration, said n+-regionlocated close to, but electrically isolated from, the source of saidpMOS transistor.
 29. The method according to claim 26 further includingthe process step of forming a body-tied source providing a dual-functioncontact region to said pMOS transistor source and to said electricallyisolated near-surface portion of said semiconductor region.
 30. Themethod according to claim 26 further including the process step offorming an angular-structured gate, configured to include an H-shape ora T-shape such that its directly adjacent regions provide contacts tosaid source, drain, and near-surface portion of said semiconductorregion.
 31. The method according to claim 26 comprising the modifiedprocess step of implanting said p-doping ions at high energy after saidprocess step of implanting said p-doping ions at medium energy.
 32. Themethod according to claim 26 wherein said n-type semiconductor has apeak doping concentration between 4·10E17 and 1·10E18 cm-3 after saidbackground doping adjustment implant.
 33. The method according to claim26 wherein said implanting of low energy ions comprises ions having anenergy suitable for creating the junction at a depth between 10 and 50nm, and a peak concentration from about 5·10E17 to 5·10E20 cm-3.
 34. Themethod according to claim 26 wherein said implanting of medium energyions comprises ions having an energy suitable for creating the junctionat a depth between 50 and 200 nm, and a peak concentration from about5·10E19 to 5·10E20 cm-3.
 35. The method according to claim 26 whereinsaid implanting of high energy ions comprises ions selected in theenergy range from about 400 to 700 keV such that the peak concentrationis at a different depth than that of the n-type semiconductor, and inthe dose range of about 8·10E12 to 8·10E13 cm-2 to overcompensate then-type semiconductor doping and to create a region of the oppositeconductivity type at a depth of more than 200 nm.